The integration of multiple metallizations in integrated circuits or chips requires major changes in terms of the material and technological processes in order to reduce delays, capacitances and couplings between different metal tracks. The replacement of silicon dioxide with dielectrics with a low dielectric constant (known as low-k materials or interlayer dielectrics—ILD) is an imperative requirement for high densities and high-speed applications. By way of example, carbon-doped silicon dioxide, other silicon-containing materials and carbon-containing compounds are used as a replacement for silicon dioxide.
Examples of ILDs which are often used at the current time include:
ProductFirmMaterial typeXLKDow CorningHydrogen silsesquioxane (HSQ)9-2222 (Boss)Dow CorningHSQ/MSQ (methylsilsesquioxane)LKD5109JSRMSQZirkonShipleyMSQSiLK/p-SiLKDow ChemicalOrganic compound; Si-(Version 1-9)containing
Black Diamond (I/II) Applied Material also contains silicon.
Almost all low-k materials used contain silicon compounds. Exceptions include, for example, SiLK and p-SiLK (p=porous), which are purely organic compounds, and fluorinated hydrocarbons.
These materials are applied during chip production and serve as separating layers between metallization levels. These layers are also known as “interlayer dielectrics” (ILD). They are also referred to as “intermetal dielectric” (IMD) or “low-k layers”.
During chip production, recesses are etched into these ILDs and are in turn filled with a metallic material so that they function as metallic interconnects. In addition, the metal tracks are also vertically connected to one another. This is achieved by the above-mentioned recesses being etched down to the metal track below at these contact locations. Additional auxiliary layers formed from silicon nitride and/or SiC are often also required, for example as an etching stop layer, as an etching mask or as a protective layer. The method described forms part of the prior art and is referred to as the dual Damascene process.
Intrinsic bubbles, that is to say cavities, which are formed during hardening by means of heating of the applied ILD layers, occur in particular in the abovementioned low-k ILD materials.
In the course of subsequent method steps which are customary during chip production and represent a thermal and/or mechanical load on the ILD material (e.g. etching, chemical mechanical polishing (CMP) or the like), these pores can form even larger cavities as a result of individual pores being connected to one another by passages. In particular at the inner wall regions of the recesses etched into these materials, surface-exposed pores, and therefore pores which are connected by passages, are exposed to contaminating chemical substances without any protection. In the context of chip production, the materials with a low dielectric constant then come into contact with various materials, for example water, atmospheric humidity or other chemicals, and these substances can penetrate into the cavities, thereby having an adverse effect or even destroying the actual function of the interlayer dielectrics (ILDs).
It is of considerable interest with a view to the integration of porous materials in particular in the back end of line (BEOL) part of chip production to prevent the penetration of contaminating substances into the porous material. The term back end of line is to be understood as meaning that part of chip production in which the electrical components, i.e. for example transistors, capacitors, etc., are wired. For this purpose, the electrical components are connected to one another in three dimensions by means of contacts (vias) and metal tracks (metal trenches). By contrast, the front end of line of chip production involves fabrication of the electrical components.
In the context of sealing surface-exposed pores in silicon-containing materials, it is already known to convert siloxane polymers into SiO2 by means of ozone (M. Ouyang et al., Chem. Mater., 12 (2000) 1591).
EP 1 138 732 A2, EP 1 122 278 A2 and JP-1149879 A1 (Patent Abstracts of Japan) describe polymer compounds which contain Si-containing organic constituents and benzotriazole constituents. DE 4107664 A1 describes compositions which may contain Si-containing organic compounds and, as further constituents, benzotriazole.
WO 01/54190 A1 describes a method for filling contact openings and recesses (trenches, vias) with copper during chip production, in which the side walls of recesses etched into low-k materials are provided with an additional dielectric layer. Oxides, such as germanium oxide, silicon dioxide, nitrogen-containing silicon dioxide, nitrogen-doped silicon dioxide, silicon oxynitride and oxynitrides, are mentioned as examples of dielectric materials. Titanium oxide, tantalum oxide, barium strontium titanate and the like are also mentioned. Materials with a low dielectric constant which can be applied to the inner walls are also mentioned. A drawback of this method, in the case of deposition of materials with a low dielectric constant, is that once again materials with an intrinsic porosity are introduced. Moreover, the additional deposition narrows the recess, and consequently the recesses have to be made wider from the outset, which runs contrary to the aim of miniaturization for future technology generations.
A further drawback is that on account of the conformal deposition required, once again it is only possible to use CVD-type processes, which makes the chip production process more complicated and also runs the risk of the precursor compounds of this CVD material being able to penetrate into the pores.
Therefore, it would be desirable to provide a possible way of protecting the inner walls of recesses etched into materials with a low dielectric constant from the penetration of harmful chemical substances into surface-exposed pores during the chip production process, which could have an adverse effect on the dielectric properties of the ILD material.
Furthermore, it would be desirable to avoid diffusion or transfer of copper ions into the interlayer dielectric and to ensure the optimum possible contact or seating of the copper filling in the trenches.